Programmable integrated circuits (ICs) are often used to implement digital logic operations according to user configurable input. Example programmable ICs include complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). CPLDs often include several function blocks that are based on a programmable logic array (PLA) architecture with sum-of-products logic. A configurable interconnect matrix transmits signals between the function blocks.
One type of FPGA includes an array of programmable tiles. The programmable tiles comprise various types of logic blocks, which can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), bus or network interfaces such as Peripheral Component Interconnect Express (PCIe) and Ethernet and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
In some programmable ICs, configuration memory cells are organized by frames for addressing configuration memory cells for purposes of programming and reading back the states of the configuration memory cells. A frame is the smallest quantity of configuration memory cells that can be programmed, and the configuration memory cells of a frame control many tiles of an FPGA. That is, in order to program certain configuration memory cells of a frame, all the configuration memory cells in the frame need to be programmed, which affects all the tiles covered by the frame.
A partially configurable portion of a circuit design refers to one or more modules for which a configuration bitstream can be generated and used to partially configure the FPGA. The remaining modules of the design are not required for the partially configurable portion of the design to be initially implemented on the FPGA. A partially reconfigurable portion of the design refers to one or more modules that have different implementations in separate configuration bitstreams. For a partially reconfigurable portion of the design, the FPGA is configured with a first bitstream to implement a first version of the partial reconfiguration (PR) modules. Subsequently, the FPGA is partially reconfigured to implement a second version of the PR modules. A static portion of the circuit design refers to one or more modules that are not subject to partial reconfiguration once implemented on the FPGA. A partially configurable portion may be static if it is not subject to partial reconfiguration.
A conventional design process begins with the creation of the design. The design specifies the function of a circuit at a schematic or logic level and may be represented using various hardware description languages (e.g., VHDL, ABEL, or Verilog) or schematic capture programs. The design is synthesized to produce a logical network list (“netlist”), and the synthesized design is mapped onto primitive components within the target device (e.g., programmable logic blocks of an FPGA).
Following mapping, placement of the components of the synthesized and mapped design is performed for the target device. During placement, each mapped component of the design is assigned to a physical position on the device. The placer attempts to place connected design objects in close physical proximity to one another in order to conserve space and increase the probability that the required interconnections between components will be successfully completed by the router. Placing connected components close to one another also generally improves the performance of the circuit since long interconnect paths are associated with excess capacitance and resistance, resulting in longer delays and greater power consumption.
Specified connections between components of the design are routed within the target device for the placed components. The routing process specifies physical wiring resources that will be used to conduct signals between pins of placed components of the design. For each connection specified in the design, the routing process allocates wire resources necessary to complete the connection. As used herein, the selection and assignment of wire resources in connecting the output pin of one component to the input pin of another component is referred to as routing a net.